1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of testing a circuit, and more particularly relates to a circuit for detecting a leakage current of a transistor used for a data processing circuit in a driver IC for a displaying apparatus.
2. Description of Related Art
A semiconductor integrated circuit is required to attain a smaller size and a higher function from year to year and to treat a large quantity of data at a high speed. For this reason, a circuit configuration is highly integrated, and a micro leakage current may result in a fatal wound of a product. Before a product is shipped, rejecting this micro current is duty of a manufacturer. Thus, it becomes necessary to design a circuit for attaining the rejection.
As the foregoing semiconductor integrated circuit, for example, a data processing circuit in a driver IC for a displaying apparatus is known. A typical measuring method of a leakage current of a ROM decoder included in the data processing circuit will be described below. FIG. 1 is a schematic view showing the typical measuring method of the leakage current of the ROM decoder. Here, FIG. 1 shows, as an example, the measuring method of the leakage current of the ROM decoder with a P-type 2-bit 4-gradation specification. A (P-type) ROM decoder 103 is provided with (P-type) enhancement type transistors 106 and (P-type) depletion type transistors 107, which are arranged in the shape of a matrix. Moreover, those transistors constitute series circuits in a row direction, and their one ends are connected to the respective connection points of a ladder resistor 101. The transistor gates of respective columns are commonly connected. Data signals DA, DB are supplied to the odd-numbered columns, and the inversion signals /DA, /DB of the data signals DA, DB are supplied to the even-numbered columns. One series circuit for selecting a gradation voltage from the ladder resistor 101 is selected by using these signals. A voltage of a power source 121 is supplied to the thus-selected series circuit, and this is also supplied to both ends of the other series circuits. Thus, it is possible to select the leakage current inside the ROM decoder 103.
In relation to the measuring method of the leakage current of the ROM decoder, Japanese patent publication No. JP-A-Heisei 11-264855 (Japanese Patent No. 3186688) discloses an integrated circuit apparatus. FIG. 2 is a schematic view showing a configuration of the integrated circuit apparatus in JP-A-Heisei 11-264855. This integrated circuit apparatus includes ladder resistors (101, 102), ROM decoders (103, 104) and a test circuit (105). In the ladder resistor 101, a predetermined number of resistors RP1 to RP63 are connected in series, compensation power source voltages V1 to V5 are supplied to at least one of connection points PP1 to PP64 of the resistors RP1 to RP63, and gradation voltages are generated at all of the connection points. Data signals are supplied to the ROM decoder 103, and one gradation voltage from the ladder resistor 101 is selected. The test circuit 105 measures a leakage current of the ROM decoder 103. The test circuit 105 has a shorting means 112 for shorting the predetermined number of the respective resistors RP when the leakage current is measured.
Similarly, in the ladder resistor 102, a predetermined number of resistors RN1 to RN63 are connected in series, compensation power source voltages V6 to V10 are supplied to at least one of connection points PN1 to PN64 of the resistors RN1 to RN63, and gradation voltages are generated at all of the connection points. Data signals are supplied to the ROM decoder 104, and one gradation voltage from the ladder resistor 102 is selected. The test circuit 105 measures a leakage current of the ROM decoder 104. The test circuit 105 has a shorting means 113 for shorting the predetermined number of the respective resistors RN when the leakage currents are measured.
That is, this integrated circuit apparatus, when measuring the respective leakage currents inside the P-type ROM decoder 103 and the N-type ROM decoder 104, executes the following measuring method. At first, when the leakage current inside the P-type ROM decoder 103 is measured, the respective division resistors RP1 to RP63 inside the ladder resistor 101 are shorted through shorting transistors 112 connected in parallel. Then, a test voltage VTP is supplied from terminals V1, V5 through a current meter to both ends of the ladder resistor 101. Consequently, the test voltage is supplied to all of the connection points PP1 to PP64 between the division resistors RP1 and RP63. At this time, since a data signal for testing is supplied from a fore-stage circuit inside the integrated circuit apparatus to the P-type ROM decoder 103, the leakage current of the P-type ROM decoder 103 can be measured by the current meter at a high precision. Similarly, when a leakage current inside the N-type ROM decoder 104 is measured, the respective division resistors RN1 to RN63 inside the ladder resistor 102 are shorted through shorting transistors 113 connected in parallel. Then, a test voltage VTN is supplied from terminals V6, V10 through a current meter to both ends of the ladder resistor 102. Consequently, the test voltage is supplied to all of the connection points PN1 to PN64 between the division resistors RN1 and RN63. At this time, since a data signal for testing is supplied from a fore-stage circuit inside the integrated circuit apparatus to the N-type ROM decoder 104, the leakage current of the N-type ROM decoder 104 can be measured by the current meter at the high precision.
As a related technique, Japanese patent publication No. JP-A-Heisei 10-213616 discloses a technique of a liquid crystal driving integrated circuit and a testing method of the same. This liquid crystal driving integrated circuit includes a plurality of liquid crystal driving output circuits, a plurality of liquid crystal driving output terminals, and a test control circuit. Each of the plurality of liquid crystal driving output circuits is composed of an operation amplifying circuit. The plurality of liquid crystal driving output terminals is connected to the respective output nodes of the plurality of liquid crystal driving output circuits, correspondingly thereto. The test control circuit divides the plurality of liquid crystal driving output circuits into a plurality of groups so as to create combinations of the partial liquid crystal driving output circuits. Each combination includes a part of the plurality of the liquid crystal driving output circuits, corresponding to output terminals. The output terminals are intermittently selected from the plurality of liquid crystal driving output terminals such that the output terminals adjacent to each other are not included. The test control circuit, then, selects groups from the plurality of groups at the time of the current leakage test, and controls the liquid crystal driving output circuits belonging to the selected groups to the high output impedance states, respectively, and also controls the liquid crystal driving output circuits adjacent to the liquid crystal driving output circuits belonging to the selected groups to the output states of the constant voltages, respectively.
I have now discovered the following facts.
In the above technique, as for the leakage current inside the ROM decoder, the two or more power sources are set to the same voltage, and the leakage current of each gradation line is measured through the ladder resistor linked to the ROM decoder. For example, in FIG. 1, as for the leakage current inside the ROM decoder 103, the two power sources 121, 122 are set to the same voltage, and the leakage current of each gradation line is measured through the ladder resistor 101 linked to the ROM decoder. Also, in FIG. 2, for example, as for the leakage current inside the ROM decoder 103, the terminals V1, V5 (the two power sources) are set to the same voltage VTP, and the leakage current of each gradation line is measured through the shorting transistor 112 linked to the ROM decoder 103.
However, in the foregoing measuring methods, the same potential is generated between the source and the drain of the transistor configuring the ROM decoder. Thus, there is a problem that a leakage current between the source and the drain cannot be measured in the case when the transistor is in an off-state.